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7-53 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 407-727-9207 | copyright ? intersil corporation 1999 HIP5061 7a, high ef?ciency current mode controlled pwm regulator description the HIP5061 is a complete power control ic, incorporating both the high power dmos transistor, cmos logic and low level analog circuitry on the same intelligent power ic. the standard boost, buck-boost, cuk, forward, flyback and the sepic (single-ended primary inductance con- verter) power supply topologies may be implemented with this single control ic. over-temperature and rapid short-circuit recovery circuitry is incorporated within the ic. these protection circuits disable the drive to the power transistor to protect the transistor and insure rapid restarting of the supply after the short circuit is removed. as a result of the power dmos transistors current (7a at 30% duty cycle, 5a dc) and 60v capability, supplies with output power over 50w are possible. ordering information part number temperature range package HIP5061ds 0 o c to +85 o c 7 lead staggered gullwing sip features ? single chip current mode control ic ? 60v, on-chip dmos power transistor ? thermal protection ? over-current protection ? 250khz operation ? output rise and fall times - 10ns ? on-chip reference voltage - 5.1v ? slope compensation ?v dd clamp allows 10.8v to 60v supply ? supply current does not increase when power device is on applications ? distributed / board mounted power supplies ? dc - dc converter modules ? voltage inverters ? small uninterruptable power supplies ? cascode switching for off line smps file number 3390.2 april 1994 pinout HIP5061 (sip) top view pin 7 v dd pin 6 v g pin 5 drain pin 4 source pin 3 fb pin 2 v c pin 1 gnd (tab) source do not use simpli?ed functional diagram slope compensation 5.1v reference gate driver control logic v dd clamp v dd HIP5061 clock over temp under voltage v/i amp v c fb gnd drain v g source v out v in 2.5v (tab)
7-54 speci?cations HIP5061 absolute maximum ratings (note 1) thermal information dc supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 16v dc supply current, i dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105ma dmos drain voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 60v average dmos drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . 5a dmos source voltage, v source , tab . . . . . . . . . . . . -0.1v to 0.1v dc supply voltage, v g . . . . . . . . . . . . . . . . . . . .-0.3v to v dd + 0.3v compensation pin current, i vc . . . . . . . . . . . . . . . . . -5ma to 35ma voltage at all other pins. . . . . . . . . . . . . . . . . . .-0.3v to v dd + 0.3v operating junction temperature range. . . . . . . . . . . 0 o c to +105 o c storage temperature range . . . . . . . . . . . . . . . . . -55 o c to +150 o c esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . class 2 - 2kv single pulse avalanche energy rating, m s (note 2) . . . eas 100mj thermal resistance q jc plastic sip package . . . . . . . . . . . . . . . . . . . . . . . . 2 o c/w maximum package power dissipation at +85 o c (depends upon mounting, heat sink and application) . . . . . 10w max. junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . . +105 o c (controlled by thermal shutdown circuit) lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . +265 o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. electrical speci?cations v dd = v g =12v, v c = 5v, v fb = 5.1v, source = gnd = drain = 0v, t j = 0 o c to +105 o c, unless otherwise speci?ed symbol parameter test conditions min typ max units device parameters i dd quiescent supply current v dd = v g = 13.2v, v c = 0v, v fb = 4v 61218ma i dd operating supply current v dd = v g = 13.2v, v c = 8.5v, v fb = 4v - 24 31 ma iv g quiescent current to gate driver v dd = v g = 13.2v, v c = 0v - 0 10 m a iv g operating current to gate driver v c = 3v - 1 2 ma v ddc clamp voltage i dd = 100ma 13.3 14 15 v v ref reference voltage i vc = 0 m a, v c = v fb 5.0 5.1 5.2 v amplifiers |i fb | input current v fb = v ref - -0.85 0.5 m a g m (v fb )v fb transconductance i vc /(v fb - v ref ) /i vc / = 500 m a, note 3 20 30 43 ms iv cmax maximum source current v fb = 4.6v -4 -1.8 -1 ma iv cmax maximum sink current v fb = 5.6v 1 1.8 4 ma a ol voltage gain /i vc / = 500 m a, note 3 44 50 - db v cmax short circuit recovery compara- tor rising threshold voltage 5.4 6.6 8.9 v v chys short circuit recovery comparator hysteresis voltage 0.7 1.1 1.8 v ivc over v c over-voltage current v dd = v g = 10.8v, v c = v cmax 01025ma clock fq internal clock frequency 210 250 290 khz dmos transistor r ds (on) drain-source on-state resistance i drain = 5a, v dd = v g = 10.8v t j = +25 o c - 0.15 0.22 w r ds (on) drain-source on-state resistance i drain = 5a, v dd = v g = 10.8v t j = +105 o c - - 0.33 w i dss drain-source leakage current v drain = 60v - 0.5 10 m a i dsh average drain short circuit current v drain = 5v, note 4 - - 5 a c drain drain capacitance note 4 - 200 - pf
7-55 speci?cations HIP5061 current controlled pwm g m (v c ) d i drain, peak / d v c note 3 1.4 2.2 3.0 a/v v/i ref voltage to current converter ref- erence voltage i drain = 0.25a, note 3 2.4 2.8 3.1 v t bt current comparator blanking time note 3 40 100 175 ns t onmin minimum dmos on time note 3 60 150 250 ns t offmin minimum dmos off time note 3 40 125 200 ns minci minimum controllable dmos peak current note 3 - 100 250 ma maxci maximum controllable dmos peak current duty cycle = 6% to 30%, note 3 7 9.5 12 a maxci maximum controllable dmos peak current duty cycle = 30% to 96%, note 3 5 8 12 a current compensation ramp d i/ d t compensation ramp rate d i drain, peak / d time, note 3 -1.4 -0.85 -0.45 a/ m s t rd compensation ramp delay note 3 1.3 1.5 1.8 m s start-up v ddmin rising v dd threshold voltage v fb = 4v 9.3 10.3 10.8 v v ddhys power-on hysteresis v fb = 4v 0.3 0.45 0.6 v v cen enable comparator threshold voltage 1.0 1.5 2.0 v r vc power-up resistance 4v < v dd < 10.8v, v c = 0.8v 50 500 3000 w thermal monitor t j substrate temperature for thermal monitor to trip note 4 105 - 145 o c t jhy temperature hysteresis note 4 - 5 - o c notes: 1. all voltages relative to pin 1, gnd. 2. v d = 10v, starting t j = +25 o c, l = 4mh, i peak = 7a. 3. test is performed at wafer level only. 4. determined by design, not a measured parameter. electrical speci?cations v dd = v g =12v, v c = 5v, v fb = 5.1v, source = gnd = drain = 0v, t j = 0 o c to +105 o c, unless otherwise speci?ed (continued) symbol parameter test conditions min typ max units table 1. conditions for unclamped energy circuit v d (v) i l (peak amps) l (mh) eas (mj) 10 5 40 550 10 7 4tz 120 6 10 0.33 18 6 12.5 0.14 12 note: device selected to obtain peak current without clocking figure 1. unclamped energy test circuit vary t p to obtain required peak i l 12v t p 7 1 i l v d + - l HIP5061
7-56 HIP5061 de?nitions of electrical speci?cations refer to the functional block diagram of figure 1 for loca- tions of functional blocks and devices. device parameters i dd , quiescent supply current - supply current with the chip disabled. the clock, error ampli?er, voltage-to-current converter, and current ramp circuits draw only quiescent current. the supply voltage must be kept lower than the turn-on voltage of the v dd clamp or else the supply current increases dramatically. i dd , operating supply current - supply current with the chip enabled. the error ampli?er is drawing its maximum current because v fb is less than its reference voltage. the voltage-to-current ampli?er is drawing its maximum because v c is at its maximum. the ramp circuit is drawing its maxi- mum because it is not being disabled by the dmos transis- tor turning off. iv g , quiescent gate driver current - gate drivers supply current with the ic disabled. the gate driver is not toggling and so it draws only leakage current. iv g , operating gate driver current - gate drivers supply current with the ic enabled. the dmos transistor drain is loaded with a large resistor tied to 60v so that it is swinging from 0v to 60v during each cycle. v ddc , v dd clamp - v dd voltage at the maximum allowed current through the v dd clamp. v ref , reference voltage - the voltage on fb that sets the current on v c to zero. this is the reference voltage for the dc/dc converter. ampli?ers |i fb |, input current - current through fb pin when it is at its normal operating voltage. this current must be considered when connecting the output of a dc/dc convertor to the fb pin via a resistor divider. g m (v fb ), transconductance - the change in current through the v c pin divided by the change in voltage on fb. the g m times the resistance between v c and ground gives the voltage gain of the error ampli?er. iv cmax , maximum source current - the current on v c when fb is more than a few hundred millivolts less than v ref . iv cmax , maximum sink current - the current on v c when fb is more than a few hundred millivolts more than v ref . a ol , voltage gain - change in the voltage on v c divided by the change in voltage on fb. there is no resistive load on v c . this is the voltage gain of the error ampli?er when g m times load resistance is larger than this gain. v cmax , v c rising threshold - the voltage on v c that causes the voltage-to-current ampli?er to reach full-scale. when v c reaches this voltage, the v c nmos transistor (tran- sistor with its drain connected to the v c pin in the functional block diagram of figure 2) turns on and tries to lower the volt- age on v c . v chys ,v cmax hysteresis - the voltage on v c that causes the nmos transistor to turnoff if it had been turned on by v c exceeding v cmax . at this voltage the current out of the voltage- to-current converter is at roughly three quarters of full-scale. ivc over ,v c over-voltage current - the current drawn through the v c pin after the nmos transistor is turned on due to excessive voltage on v c . the nmos transistor con- nected to the v c pin draws more than enough current to overcome the full scale source current of the error ampli?er. clock fq, frequency - the frequency of the dc/dc converter. the clock actually runs faster than this value so that various con- trol signals can be internally generated. dmos transistor r ds(on) , on resistance - resistance from dmos transis- tor drain to source at maximum drain current and minimum gate driver voltage, v g . i dss , leakage current - current through dmos transistor at the maximum rated voltage. current controlled pwm g m (v c ), transconductance - the change in the dmos tran- sistor peak drain current divided by the change in voltage on v c . when analyzing dc/dc converters the dmos transistor and the inductor tied to the drain are sometimes modelled as a voltage-controlled current source and this parameter is the gain of the voltage-controlled current source. v/i ref , current control threshold - the voltage on v c that causes the dmos transistor to shut off at the minimum controllable current. this voltage is greater than the enable comparator threshold (v cen ) so that as v c rises the ic does not jump from the disabled state to the dmos transis- tor conducting a large current. t bt , blanking time - at the beginning of each cycle there is a blanking time that the dmos transistor turns-on and stays- on no matter how high drain the current. this blanking time permits ringing in the external parasitic capacitances and inductances to dampen and for the charging of the reverse bias on the recti?er diode. t onmin , minimum dmos transistor on time - the mini- mum on-time for the dmos transistor where small changes in the v c voltage make predictable changes in the dmos transistor peak current. converters should be designed to avoid requiring pulse widths less than the minimum on time. t offmin , minimum dmos transistor off time - the min- imum off-time for the dmos transistor that allows enough time for the ic to get ready for the next cycle. converters should be designed to avoid requiring pulse widths so large that the mini- mum off time is violated. (however, zero off time is allowed, that is, the dmos transistor can stay on from one cycle to the next.) minci, minimum controllable current - when the voltage on v c is below v/i ref , the peak current for the dmos tran- sistor is too small for the current comparator to operate reli- ably. converters should be designed to avoid operating the dmos transistor at this low current.
7-57 HIP5061 maxci, maximum controllable current - the peak current for the dmos transistor when the voltage-to-current con- verter is at its full scale output. the dmos transistor current may exceed this value during the blanking time so proper precautions should be taken. this parameter is unchanged for the ?rst 3/8 of the cycle and then decreases linearly with time because of the current ramp becoming active. current compensation ramp d i/ d t, compensation ramp rate - at a given voltage on v c the dmos transistor will turn off at some current that stays constant for about the ?rst 1.5 m s of the cycle. after 1.5 m s, the turnoff current starts to linearly decrease. this parameter speci?es the change in the dmos transistor turnoff current. t rd , compensation ramp delay - the time into each cycle that the compensation ramp turns on. the current compen- sation ramp, used for slope compensation, is developed by the current ramp block shown in the functional block diagram of figure 2. start-up v ddmin , rising v dd threshold voltage - the minimum voltage on v dd needed to enable the ic. v ddhys , power - on hysteresis voltage - the difference between the voltage on v dd that enables the ic and the volt- age that disables the ic. v cen , enable comparator threshold voltage - the mini- mum voltage on v c needed to enable the ic. the ic can be shutdown from an open-collector logic gate by pulling down the v c pin to gnd. r vc , power - up resistance - when v dd is below v ddmin , the nmos transistor connected to the v c pin is turned on to make sure the v c node is low. thus the voltage on v c can gradually build up as will the trip current on the dmos tran- sistor. this is the only form of soft start included on the ic. the resistance is measured between the v c and gnd pins. thermal monitor t j , rising temperature threshold - the ic temperature that causes the ic to disable itself so as to prevent damage. proper heat-sinking is required to avoid over-temperature conditions, especially during start-up when the dmos tran- sistor may stay on for a long time if an external soft-start cir- cuit is not added. t jhy , temperature hysteresis - the ic must cool down this much after it is disabled by being too hot before it can resume normal operation. figure 2. functional block diagram of the HIP5061 gate driver bias current monitoring v g v ref = 5.1v v dd v dd source drain 7 tab 6 5 circuits + - + - source control clock 4 enable error amp thermal monitor ramp current compare 1.5v 5.1v 2k w 360 w HIP5061 current + - + - 7.0v short v dd monitor 10.3v + - blanking enable 2k w current sample ramp enable ramp reset error current 100ns under voltage v dd error disable gnd 1 v ref amp 360 w circuit logic internal lead inductance and resistance lock out v c 2 fb 3 v dd clamp band gap reference regulator + - voltage to current converter light load comparator
7-58 HIP5061 pin description terminal number designation description 1 gnd this is the analog ground terminal of the ic. 2v c the output of the transconductance ampli?er appears at this terminal. input to the internal voltage to current converter also appears at this node. transconductance ampli?er gain and loop response are set at this terminal. when the v dd terminal voltage is below the starting voltage, v ddmin , this terminal is held low. when the voltage at this terminal exceeds v cmax , 7v typical, implying an over-current condition, a typical 10ma current, i vcover pulls this terminal towards ground. this current remains on until the voltage on the v c terminal falls by v chys , typically 1.1v, below the upper threshold, v cmax . when the voltage on this terminal falls below v cen , typically 1.5v, the ic is disabled. 3 fb feedback from the regulator output is applied to this terminal. this terminal is the input to the transconductance ampli?er. the ampli?er compares the internal 5.1v reference and the feedback signal from the regulator output. 4 source the terminal, labeled tab, has a connection to this terminal, but because of the long lead length and resulting high inductance of this terminal, it should not be used as a means of bypassing. therefore, this terminal is labeled do not use. 5 drain connection to the drain of the internal power dmos transistor is made at this terminal. 6v g gate drive supply voltage is provided at this terminal. a 10 w to 150 w resistor connected between this terminal and the v dd terminal provides decoupling and the supply voltage for the gate drivers. 7v dd external supply input to the ic. a nominal 14v shunt regulator is connected between this terminal and the tab. a series resistor should be connected to this terminal from the external voltage source to supply a minimum current of 33ma and a maximum current of 105ma under the worst cast supply voltage. the series resistor is not required if the supply voltage is 12v, 10%. tab source this is the internal power dmos transistor source terminal. it should be used as the ground return for the v dd bypass capacitor. in addition high frequency bypassing for both the regulator output load voltage and supply input voltage should be returned to this terminal. for more information refer to application notes an9208, an9212, an9323. foot print for soldering to-220 staggered gull wing sip limit of solder mask for header 0.050 typ 0.050 typ 0.080 typ optional ? 0.151 0.523 0.480 0.575 0.675 0.120 0.212 0.424
7-59 HIP5061 typical performance curves figure 3. typical supply current vs temperature figure 4. typical supply current vs supply voltage figure 5. typical gate driver operating current vs temperature figure 6. typical supply current vs voltage at pin v c for 0 o c and +105 o c figure 7. typical clamp voltage vs temperature figure 8. typical reference voltage vs temperature 0 10 20 30 40 50 60 70 80 90 100 6 8 10 12 14 16 18 20 22 24 26 ambient temperature ( o c) supply current (ma) operating current, v dd = v g = 13.2v, v c = 8.5v, v fb = 4v quiescent current, v dd = v g = 13.2v, v c = 0v, v fb = 4v 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v dd (v) 20 18 16 14 12 10 8 6 4 2 0 supply current (ma) v fb = v c = 0v, t a = +25 o c 0 10 20 30 40 50 60 70 80 90 100 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 ambient temperature ( o c) gate driver current (ma) v dd = v g = 12v, v fb = 5.1v, v c = 5v 0 1 2 3 4 5 6 7 8 9 10 11 12 voltage at v c pin (v) 26 24 22 20 18 16 14 12 10 8 6 4 supply current (ma) t a = +105 o c t a = 0 o c v dd = 12v, v fb = 6v 0 10 20 30 40 50 60 70 80 90 100 13.0 13.2 13.4 13.6 13.8 14.0 14.2 14.4 14.6 14.8 15.0 ambient temperature ( o c) clamp voltage (v) i dd = 100ma 0 10 20 30 40 50 60 70 80 90 100 5.00 5.02 5.04 5.06 5.08 5.10 5.12 5.14 5.16 5.18 5.20 ambient temperature ( o c) reference voltage (v) v dd = v g = 12v, i vc = 0 m a, v c = v fb
7-60 HIP5061 figure 9. typical reference voltage vs supply voltage for 0 o c and +105 o c figure 10. typical input current to fb pin vs temperature figure 11. typical input current to fb pin vs v fb figure 12. typical error amplifier transconductance vs temperature figure 13. typical v c pin current iv c pin vs voltage on fb pin (shows error amplifier transconductance) figure 14. typical error amplifier sinking and sourcing current vs temperature typical performance curves (continued) 10.8 11.2 11.6 12.0 12.4 12.8 13.2 13.6 14.0 5.00 5.02 5.04 5.06 5.08 5.10 5.12 5.14 5.16 5.18 5.20 v dd (v) reference voltage (v) t a = 0 o c t a = +105 o c i vc = 0ma, v c = v fb 0 10 20 30 40 50 60 70 80 90 100 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 ambient temperature ( o c) input current (na) v dd = v g = 12v, v c = 5v, v fb = v ref -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 voltage on fb pin (v) 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 input current ( m a) v dd = v g = 12v, v c = 4v, t a = +25 o c 0 10 20 30 ambient temperature ( o c) 50 60 70 80 90 100 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 40 error amplifier transconductance (ms) v dd = v g = 12v, iv c = 500 m a -175 -150 -125 -100 -75 -50 -25 0 25 50 75 100 125 150 175 voltage on fb pin (mv) centered around 5.1v 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 v c pin current (ma) v dd = v g = 12v, v c = 4v, t a = +25 o c 0 10 20 30 40 50 60 70 80 90 100 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 ambient temperature ( o c) output current (ma) v dd = v g = 12v, v c = 5v sourcing current, v fb = 4.6v sinking current, v fb = 5.6v
7-61 HIP5061 figure 15. typical v c pin current vs voltage on fb pin figure 16. typical v c pin current vs voltage on v c pin for 0 o c and +105 o c figure 17. typical v c pin current vs voltage on v c pin for voltages above and below v ref figure 18. typical short circuit comparator threshold voltage vs temperature figure 19. typical over-voltage current vs temperature figure 20. typical clock frequency percent change vs temperature typical performance curves (continued) -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 voltage on fb pin (v) 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 v c pin current (ma) v dd = v g = 12v, v c = 4v, t a = +25 o c 0 1 2 3 4 5 6 7 8 9 12 10 8 6 4 2 0 voltage on v c pin (v) v c pin current (ma) t a = 0 o c t a = +105 o c v dd = 9v (under voltage condition) 0 1 2 3 4 5 6 7 8 9 10 11 12 -4 -2 0 2 4 6 8 10 12 14 16 voltage on v c pin (v) v c pin current (ma) v dd = 12v, t a = +25 o c fb = 6v fb = 4v fb = 6v fb = 4v 0 10 20 30 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 ambient temperature ( o c) v dd = vg = 12v v chys v cmax thresold and hysteresis voltage (v) 0 10 20 30 40 50 60 70 80 90 100 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 ambient temperature ( o c) over-voltage current (ma) v dd = v g = 10.8v, v c = v cmax 0 10 20 30 40 50 60 70 80 90 100 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 ambient temperature ( o c) percent frequency change v dd = v g = 12v, v fb = 5.1v
7-62 HIP5061 figure 21. typical clock frequency percent change vs supply voltage v dd at 0 o c and +100 o c figure 22. typical dmos transistor drain to source resistance vs temperature figure 23. typical dmos transistor drain to source resistance vs drain current i drain at 0 o c and +100 o c figure 24. typical dmos transistor drain to source leakage current vs temperature figure 25. typical transconductance from v c pin to dmos transistor drain (peak current) vs temperature figure 26. typical voltage to current converter reference voltage vs temperature typical performance curves (continued) 10.8 11.2 11.6 12.0 12.4 12.8 13.2 13.6 14.0 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v dd (v) percent frequency change t a = 0 o c t a = +100 o c v dd = v g = 12v, v fb = 5.1v 0 10 20 30 40 50 60 70 80 90 100 0.00 0.05 0.10 0.15 0.20 0.25 0.30 ambient temperature ( o c) dmos transistor drain to source resistance ( w ) v dd = v g = 10.8v, i drain = 5a 0 1 2 3 4 5 6 7 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.30 dmos transistor drain current (a) dmos transistor drain to t a = 0 o c t a = +100 o c v dd = v g = 10.8v, v fb = 5.1v source resistance ( w ) 0 10 20 30 40 50 60 70 80 90 100 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 ambient temperature ( o c) dmos traisistor leakage current ( m a) v dd = 60v 0 10 20 30 40 50 60 70 80 90 100 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 ambient temperature ( o c) transconductance (a/v) v dd = v g = 12v 0 10 20 30 40 50 60 70 80 90 100 2.74 2.76 2.78 2.80 2.82 2.84 2.86 2.88 2.90 ambient temperature ( o c) reference voltage (v) v dd = v g = 12v, i drain = 0.25a
7-63 HIP5061 figure 27. typical minimum dmos transistor on time vs temperature figure 28. typical minimum dmos transistor off time vs temperature figure 29. typical maximum controllable peak dmos drain current vs temperature figure 30. typical compensating ramp rate vs temperature figure 31. typical compensation ramp delay time vs temperature figure 32. typical rising v dd comparator threshold voltage vs temperature typical performance curves (continued) 0 10 20 30 40 50 60 70 80 90 100 140 145 150 155 160 165 170 175 180 ambient temperature ( o c) minimun dmos transistor "on" time (ns) v dd = v g = 12v ambient temperature ( o c) minimum dmos transistor "off" time (ns) 0 10 20 30 40 50 60 70 80 90 100 115 120 125 130 135 140 145 150 v dd = v g = 12v 0 10 20 30 40 50 60 70 80 90 100 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 ambient temperature ( o c) max controllable peak current (a) v dd = v g = 12v, duty cycle = 96% 0 10 20 30 40 50 60 70 80 90 100 -1.00 -0.95 -0.90 -0.85 -0.80 -0.75 -0.70 -0.65 -0.60 -0.55 -0.50 ambient temperature ( o c) compensating ramp rate (a/ m s) v dd = v g = 12v 0 10 20 30 40 50 60 70 80 90 100 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 ambient temperature ( o c) compensating ramp delay time ( m s) v dd = v g = 12v 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 5 6 7 8 9 10 11 ambient temperature ( o c) vddmin and vddhys voltage (v) v ddmin v ddhys v fb = 4v
7-64 HIP5061 typical application circuit figure 33 shows a simpli?ed block diagram of the HIP5061 in a typical boost converter. a resistor connected from the v in supply to the v dd terminal of the ic powers the internal 14v shunt regulator. the gate driver supply is decoupled from the main supply by a small external resistor connected between v dd and the v g terminal. a bypass capacitor is connected between the v dd terminal and ground to reduce coupling between analog and digital circuitry. a schottky diode insures ef?cient energy transfer from the dmos drain circuit inductor to the load. to set the output voltage, two resistors are used to scale the output supply voltage down to the 5.1v internal reference. the heart of the ic is the high current dmos power transistor with its associated gate driver and high-speed peak current control loop. a portion of the converters dc output is applied to a transconductance error ampli?er that compares the fed back signal with the internal 5.1v reference. the output of this ampli?er is brought out at the v c terminal to provide for soft start and frequency compensation of the control loop. this same signal is also applied internally to program the peak dmos transistor drain current. to assure precise current control, the response time of this peak current control loop is less than 50ns. a 2mhz internal clock provides all the timing signals for the converter operating at 250khz. a slope compensation circuit is also incorporated within the converter ic to eliminate sub- harmonic oscillation that occurs in continuous-current mode converters operating with duty cycles greater than 50%. HIP5061 description of operation figure 2 shows a more detailed functional block diagram of the HIP5061. an internal 14v shunt regulator in conjunction with an external series resistor provides internal operating voltage to the ic in applications where no 12v auxiliary sup- ply is available. note that in applications where the input voltage at v dd is 12v, +/-10%, the regulator is not used. this regulator is shown as a zener diode on the diagrams of fig- ure 2 and figure 33. the 2mhz clock is processed in the control logic block to provide various timing signals. a cycle of operation begins when a 100ns pulse (which occurs at a 4 m s interval) triggers the latch that initiates the dmos transistor on-time. this pulse also provides a blanking interval in the current moni- toring block to eliminate false turn-offs caused by high tran- sient pulse currents that occur during turn-on. the output of figure 33. simplified block diagram of the HIP5061 in a typical "boost" configuration slope compensation 5.1v reference gate driver control logic v dd clamp v dd HIP5061 2mhz over temp under voltage v/i amp v c fb gnd drain v g (source) v out v in 2.6v tab clock
7-65 HIP5061 the current ramp block is summed with the sensed dmos transistor current (to provide slope compensation) before being compared with the error current signal. the current ramp, -0.45a/ m s, is inhibited for the ?rst 1.5 m s (37.5%) of the duty cycle by the ramp enable signal, since ramp is not needed for slope compensation during this interval. inhibit- ing of the compensating ramp has the effect of reducing the peak short-circuit current. the output of the power supply is divided down and monitored at the fb terminal. a transconductance error ampli?er compares the dc level of the fed back voltage with an internal bandgap reference, while providing voltage loop compensation by means of external resistors and capacitors. the error ampli?er output (the error voltage) is then converted into a current (the error current) that is used to program the required peak dmos transistor current that produces the desired output voltage. when the sum of the sensed dmos transistor current and the compensating ramp exceed the error current signal, the latch is reset and the dmos transistor is turned off. current comparison around this loop takes place in less than 50ns, allowing for excellent 250khz converter operation. the latch can also be reset by an under-voltage (v dd < 10.3v typical), over temperature (t j > +125 o c typical) or a shutdown signal externally applied at the v c terminal. see figure 36. note that if the error voltage (at the v c pin) is less that 2.55v, then the output of the voltage-to-current converter will be held at zero. this condition will produce the minimum possible pulse width, typically 150ns (100ns blanking pulse plus 50ns delay). error voltages lower than this 2.55v level will not produce shorter pulse widths. under very light loads (when v c goes below 1.5v), the enable comparator will temporarily hold-off the pwm latch (and the dmos transis- tor) until the v c voltages rises above 1.5v. this low v c inhibit circuit results in a burst-mode of operation that main- tains regulation under light or no loads. during an over-current condition, the output of the error ampli?er will attempt to exceed the 7.0v threshold. at this point, the short-circuit comparator will pull down on this sig- nal and induce a low-level oscillation about the threshold, serving to clamp the peak error voltage. this clamping action, in turn, will limit the peak current in the dmos tran- sistor, reducing the duty ratio of the switch as the demand for current continues to increase. this action, in conjunction with the thermal monitor, serves to protect the ic from over- current (short-circuit) conditions. using the transconductance error ampli?er a transconductance ampli?er with a typical g m of 30ms is used as the input gain stage where the power supply output voltage is compared with the internally generated 5.1v reference voltage. a pnp transistor input structure allows this ampli?er to accommodate large negative going transient voltages without causing ampli?er phase reversal, often associated with pnp input structures. negative transients up to 5v applied to the input though at least 5.1k will not result in phase reversal. the ampli?er output stage has the customary drain to drain output to help improve the output impedance, ideally in?nity. the ampli?er gain is typically 50db and is not signi?cantly altered when operating into the stages that follow within the ic. to minimize the output stage idling current, while providing high peak currents to insure rapid response to load and input transients, a class b type of output stage was used in the ampli?er. placing a 100k resistor from the ampli?er output terminal, v c , to ground will bias the output stage to an active state and still minimize power consumption. in all cases, the resistor shunting the transconductance ampli?er output must be greater than 10k w to insure that the output will rise suf?ciently high to obtain the maximum dmos transistor drain current. start-up sequence upon initial power up of the HIP5061 in a typical application circuit, the voltage at v c will be zero, and the dmos transis- tor will be off. when the voltage at v dd rises above the 10.3v typical threshold, the error ampli?er output is enabled and the v c voltage begins to rise in response to the low volt- age at the fb terminal. when the v c voltage rises above 1.5v the dmos transistor begins to switch at the minimum duty cycle, and when it rises above 2.55v the duty cycle begins to increase. the v c voltage (and peak dmos tran- sistor current) will then continue to rise until the voltage loop gains control and establishes regulation. note that the rate of rise in the v c voltage can be controlled by an external soft start circuit (see soft start implementation ). if the v c voltage is unrestricted in its rate of rise, then it will typically rise quickly to its maximum (peak current) value, causing the dmos transistor to turn-on and stay on until it reaches the peak current value. at this point, the dmos transistor begins switching, and the v c voltage (and peak dmos transistor current) will drop down to the level com- manded by the voltage loop. using the shunt regulator the internal 14v shunt regulator in conjunction with an external series resistor allows the ic to operate from quite high input voltages, limited only by power dissipation in the external resistor. when only higher voltages are available, a bootstrap or other 12v auxiliary supply can be used to elimi- nate this dissipation. the series resistor should be chosen to be as large as possible to reduce power dissipation at high line, while ensuring adequate v dd voltage at low line. the maximum value for this resistor, r , is given by: where v i is the input voltage to the power supply. the value chosen for this resistor must also result in a current, i , into the v dd clamp that is less than 105ma when the input volt- age is at its maximum: r max w () v i min , 10.5 C 0.033 ---------------------------------------- - = i max a () v i max , 13.3 C ? ?? r max ------------------------------------------------- - =
7-66 HIP5061 inductor selection the selection of the energy storage inductor(s) l stor for a dc to dc converter has tremendous in?uence on the behavior of the converter. it is particularly important in light of the high level of integration (and necessarily few degrees of freedom) achieved in the HIP5061. there are several factors in?uencing the selection of this inductor. first, the inductance of l stor will determine the basic mode of operation for the converter: continuous or discontinuous current. in order to maximize the output power for the given maximum controllable dmos transistor current, a converter may be designed to operate in continuous current mode (ccm). however, this tends to require a larger inductor, and for many converter topologies results in a feedback loop tha is dif?cult to stabilize. for these and other reasons, the inductor l stor may be chosen so as to operate the converter in discontinuous current mode (dcm). the relative merits of ccm and dcm operation for various topologies and the corresponding selection of l stor is well documented and will not be covered here. a second factor in?uencing the selection of l stor is the stability requirement for current-mode control. this constraint is only applicable for converters operating in ccm, since open- loop instabilities of this type are not observed in converters operating in dcm. for marginal stability, the compensating ramp (internal to the HIP5061) must have a slope that is greater than one-half the difference between the inductor currents down slope and up slope. (to ensure stability for duty ratios d > 0.8, the slope of the compensating ramp should be equal to the inductor current downslope.) a generally accepted goal is to set the slope of the compensating ramp to be at least one-half of the inductor current down slope. since there is no external control over the internal compensating ramp, one must be sure that the inductor is large enough so that the down slope of the inductor current is not too large. table 2 summarizes this requirement for minimum inductance for several common topologies. a third constraint on the size of the inductor is one that is common among current-mode controlled pwm converters, and applies to both dcm and ccm operation. the stable generation of the desired dmos transistor pulse width depends on the accurate comparison of the error signal and the peak l stor (dmos) transistor drain current. thus, as the peak l stor ripple current becomes smaller, immunity from noise on the error signal is eventually reduced until the pulse width can no longer be adequately controlled. for the HIP5061, the inductor current ripple must be at least 200ma peak to peak to ensure proper control of the dmos transistor current. this effectively establishes a maximum value for the inductor l stor , so as to maintain at least 200ma of ripple. note that under extremely light or no load conditions, all converters will eventually operate in dcm, and the 200ma requirement will eventually be violated. under these conditions, the HIP5061 will continue to regulate, although the switching of the dmos transistor will be in a burst-mode, controlled by the light load comparator. (see figure 2.) dmos transistor turn-off snubber in order to reduce dissipation in the dmos transistor due to turn-off losses, the turn-off time has been minimized. however, the rapid reduction of current that occurs in the drain of the dmos transistor can result in large transient voltages being induced across any parasitic inductance in the drain path. for this reason, it is important that such parasitic inductance be reduced by good, high frequency layout practices. nevertheless, there are many instances (e.g., transformer isolated topologies) in which voltages in excess of 60v may be developed at the dmos transistor drain. in some cases, a simple r-c snubber may be added to reduce the overshoot of the drain voltage to a safe level. it is also possible that the large amount of ringing that can occur at the dmos transistor drain at turn-off will induce noise in the ic. this noise may result in false triggering of the pwm latch, particularly at high peak dmos transistor drain currents. noise related instability can also be elimi- nated by the addition of a snubber, which will rapidly damp out such turn-off ringing. good layout practices will reduce the need for such protective measures, and ensure that the dmos transistor is not overstressed. under-voltage lockout the v dd input voltage is monitored by a comparator that holds off the dmos transistor gate drive signal when the v dd voltage is less that about 10.3v. the typical 0.5v hyster- table 2. minimum inductance for stable ccm operation above 50% duty cycle converter type minimum inductance boost sepic (note 1) cuk (note 2) flyback forward notes: 1. assumes that l 1 and l 2 are both ccm. 2. l = inductance in henrys, v o = output voltage, v d = diode voltage drop, v i = input voltage, m r,min = ( d i/ d t) min = 0.45a/ m s, l 1 = drain inductor, l 2 = secondary inductor, n p = primary turns, n s = secondary turns l v o v d v i ,min C + 2 m r ,min ------------------------------------------- - = l 1 l 2 l 1 l 2 + ----------------- - v o v d + 2 m r ,min ---------------------- - > l 1 l 2 l 1 l 2 + ----------------- - v o v d C 2 m r ,min ---------------------- - > l p n p n s ------- ? ? ?? v o v d + () 2 m r ,min --------------------------- - > l n s n p ------- ? ? ?? v o v d + () 2 m r ,min --------------------------- - >
7-67 HIP5061 esis of this comparator is intended to reduce oscillation when the voltage at v dd is in the vicinity of 10v. note, how- ever, that when an external series resistor is used to feed the shunt regulator, the voltage drop across this resistor (which sharply decreases when the ic shuts down), effectively reduces the hysteresis. to reduce the tendency for oscilla- tion in the vicinity of the 10v threshold, the impedance of the source that feeds the dc to dc converter input should be minimized. the addition of a capacitor (1 m f-47 m f) at the v dd terminal can also help to provide smooth turn-on or turn- off of the converter if the input supply rises or falls gradually through the v dd comparator threshold. peak controllable dmos transistor current figure 34 shows the guaranteed minimum, peak controllable dmos transistor current versus duty cycle. this peak cur- rent value is established by the current limit circuitry, which effectively clamps the voltage at v c (the error voltage) to perform current limiting. since the sensed dmos transistor current is summed with a compensating current ramp that begins its rise 1.5 m s after the initiation of a cycle, current lim- iting will begin to occur at a peak dmos transistor current that varies with the operating duty cycle. the highest current limit threshold occurs for d<0.375, where no ramp is added to the sensed dmos transistor current. at higher operating duty ratios, the onset of current limit will occur at increasingly lower currents, due to the effect of adding the compensating ramp to the sensed current. note that this curve represents guaranteed minimum values. the guaranteed maximum val- ues are considerable higher, although they are still limited to levels that protect the ic. figure 34. peak dmos transistor drain current vs duty cycle when the dmos transistor ?rst turns on there may be sub- stantial current spikes exceeding the normal maximum peak current established by the current control stages within the ic. to prevent these spurious spikes from conveying errone- ous information to the current comparator, a 100ns blanking signal is applied to the current monitoring circuitry. thus, there is no peak current protection during the ?rst 6% of the duty cycle (see figure 36). duty cycle 1.0 0.06 1 3 5 7 peak dmos current (a) 0.375 dmos transistor turn-on noise although the large dmos transistor turn-on current spikes are blanked over by the control circuit, it is important to minimize these current spikes, since they often result in voltage spikes considerably below the device substrate that can activate par- asitic devices within the ic. such activation of parasitic devices will often result in improper operation of the ic. an external terminal labeled v g brings out the power supply to the gate drive circuitry. this allows for the control of the peak current delivered to the gate of the dmos transistor, which in turn establishes the turn-on speed. the v g pin may be exter- nally bypassed for the fastest possible turn-on, or series resis- tance may be added with no bypassing capacitor to slow down the turn-on of the dmos transistor. depending upon the actual layout of the supply, it is generally recommended that a series resistor be added (10 w -150 w ) so that the dmos tran- sistor turn-on speed is reduced. by properly adjusting the turn-on speed, undershoot can be avoided while turn-on switching losses are kept to a minimum. soft start implementation it is often desirable to allow the regulator to start up slowly, figure 35 shows one means of implementing this action. the normally high output current from the HIP5061 transconduc- tance ampli?er (when v fb = 0 and v ref = 5.1v) is directed to an external capacitor through a diode. this slows down the rate of rise of the voltage at the v c terminal. after the regula- tor starts, the external capacitor is charged to v dd and is effectively removed from the frequency compensation net- work by a reverse biased diode. to ensure rapid recycling of the capacitor voltage with removal of power, a diode is placed across the 100k w resistor. logic shutdown input (v c pin). figure 35. soft start circuit for the HIP5061 the dc to dc converter may be shut down by returning the v c output terminal to ground. a sinking current greater than 4ma will insure that this output is pulled to ground. it must be remembered that once switching operation ceases, the drain of the dmos transistor is open. when the supply is in the boost con?guration, the output voltage is not zero but the input voltage less diode and inductor voltage drops. if the sepic 0.1 m f 20 m f HIP5061 gate driver and control v dd v g drain fb v c gnd circuitry source soft start network typical frequency compensation network 2ma, typ 100k w 100k w
7-68 HIP5061 topology is used, this is not the case. shutting down the regu- lator via the v c terminal will cut off the output. figure 36 shows two methods of shutting down the ic. in each case the current sinking circuit must be able to sink at least 4ma, the maximum current from the HIP5061 v c terminal. figure 36. two methods of shutting down the HIP5061 mounting, layout and component selection the to-220 package with its gullwing leads was designed to be surface mounted. to aid in the external reduction of lead length and hence inductance and resistance, the ic leads were staggered. to keep the inductance and resistance of the critical drain terminal as low as possible, it is suggested that the pc trace to the dmos transistor drain terminal be made as wide as possible. the adjacent source terminal is not recommended to be used and therefore allows the metal to the drain terminal to be widened beyond the normal widths for these terminals. figure 37 illustrates these points. one of the most important aspects to the proper application of this device is high frequency bypassing. in a boost con- verter, for example, there should be a low-inductance inter- connect from the dmos transistor drain, through the output diode and capacitors, and returning to the tab (source) of the HIP5061. inductance in this line results in large transient voltages on the dmos transistor drain terminal which can result in voltages above the maximum dmos transistor drain voltage rating. figure 37. showing wider pc board metal for critical HIP5061 gate driver and control v dd v g drain fb v c gnd circuitry source 4ma from cd4049ub note: frequency compensation network not shown off off alternate method HIP5061 ground pc metal v dd pc metal v g pc metal ic soldered to pc board wider drain pc metal for lower inductance normal pc metal for fb and v c all the capacitors shown with values of 1 m f or less are of the multilayer ceramic type with the x7r dielectric material. this material has a fairly ?at voltage and temperature coef?cient that assures that the capacitance remains comparatively con- stant at extreme operating temperatures and voltages. the multilayer construction allows for comparatively large values with good volumetric ef?ciency and low inductance. capaci- tors around the power input and output circuits should be returned to the device tab via a low inductance ground plane. this tab is internally connected to the dmos transistor source. the schematic diagram of figure 38 was drawn with the diagonal leads to show the critical paths for the various high frequency elements. these short interconnects assure the lowest inductance around the output power circuit. design of a 28v, 1.8a boost converter figure 38 shows the schematic diagram and a parts list of a 50w supply designed with the HIP5061. table 3 tabulates the performance of the power supply. inductor selection in order to maximize the output power for the given maxi- mum controllable dmos transistor current, this converter has been designed to operate in continuous current mode (ccm). in this mode, the inductor value will generally be large, resulting in a lower inductor ripple current and a lower peak dmos current. to ensure that the converter operates in ccm over the usable range of input voltage and output current, the value of l2 must be greater than the critical inductance, given by table 3. typical laboratory performance of 50w, 28v/1.8a regulator input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11v to 16v line regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12mv/v output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.0v load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 64mv/a output ripple, fl . . . . . . . . . . . . . . . . . . . . . . . . . . (20mhz bw) 600mv p-p output ripple, after filter, fl . . . . . . . . . . . . . . . . . (20mhz bw) 80mv p-p efficiency: v i = 11v, i l = 0.18a. . . . . . . . . . . . . . . 90% v i = 11v, i l = 1.8a. . . . . . . . . . . . . . . . 89% v i = 16v, i l = 0.18a. . . . . . . . . . . . . . . 73% v i = 16v, i l = 1.8a. . . . . . . . . . . . . . . . 93% l crit v o v i max , 2 v o v d v imax , C + ? ?? t s 2p o min , v o v d + ? ?? 2 ----------------------------------------------------------------------------------------------------------- = 28 () 16 () 2 28 0.5 16 C + () 4 6 C 10 2 5.6 () 28 0.5 + () 2 ------------------------------------------------------------------------------------------------- - = 39 m h =
7-69 HIP5061 where p o,min has been arbitrarily chosen as 5.6w, corre- sponding to an output current of 0.2a, and v d is the forward voltage of cr1. thus, for l2 > 39 m h, the converter will be in ccm for v i = 11v to 16v and i l = 0.2a to 1.8a. a second factor in?uencing the selection of l2 is the stability requirement for current-mode control. using the above equation for l min for the boost converter: thus, l2 must be at least 19 m h to ensure good stability of the current loop, and a choice of l2 = 40 m h satis?es this requirement, while maintaining ccm operation over an extremely wide load range. the chosen core material for l2 is kool mu ferrous alloy pow- der from magnetics, inc. this material was chosen because of its relatively low cost, while its losses due to ac ?ux are ?ve to ten times less than conventional powdered iron. loop compensation the control to output transfer function for this current-mode boost converter has the following characteristics over the speci?ed load and line conditions: l v o v d v i min , C + 2m ramp min , ----------------------------------------------------- > 28 0.5 11 C + 2 0.45 6 10 a s ? ?? -------------------------------------------------------- - 19 m h == d.c. gain: 20db-40db pole at 88hz-880hz lhp zero at 1mhz rhp zero at 11.0khz-110khz double pole at 80khz (from ?lter) to stabilize the voltage loop, it is necessary to establish the unity gain crossover frequency well below the rhp zero, since this zero introduces positive gain and negative phase. a cross- over of 4khz is fairly conservative, and is achieved by adding a 1 m f capacitor at the vc pin, which provides near in?nite dc gain, and about -5db of gain at 4khz. this results in a phase margin of about 15 o at full load. note that r4 is required for proper operation of the transconductance ampli?er, since it is providing bias current for the output stage as discussed under using the transconductance error ampli?er section. output filter design inductor l3 was chosen with c11 to provide at least 15db of ripple attenuation at the switching frequency. the corner fre- quency (80khz) of this ?lter is well above the crossover fre- quency of the voltage loop (4khz), and has no effect on stability. this secondary lc ?lter was used to reduce output ripple instead of a lower-cost, high-value, low esr alumi- num electrolytic capacitor to demonstrate the reduction in volume possible at this switching frequency. a lower cost solution could achieve the same output ripple by replacing c9,10,12 and l3 with one or two large capacitors (e.g., figure 38. HIP5061 50w, 28v boost regulator schematic and parts list input drain gnd tab v c fb v g HIP5061 (source) v dd ra 2.21k, 1% 6.8 m f, 50v cr1 c1 c3 c4 c9 r1 r2 r4 r5 20 w , 1w 10 w , 1/4w gate drivers, control circuitry l2, 40 m h 10k, 1% 100k c11 l3, 4 m h output 28vdc 0a - 1.8a 1 m f, 50v 47 m f, 50v 1 m f, 50v 1 m f, 50v 1 m f, 50v 11vdc - 16vdc c13 1nf, 100v r11 c12 1 2 3 5 6 7 and logic optional filter 47 m f, 50v c5 7.5 w , 1/2w 6.8 m f, 50v c10 parts list ra 20 w , 1w, wirebound - dale rwr81s20r0fr or equivalent r1 10k, 1% r2 2.2k, 1% r4 100k, 1/4w r5 10 w , 1/4w r11 7.5 w , 1/2w, carbon - allen bradley eb75g5 c1, c3, c4 and c11 1 m f, 50v, ceramic - murata erie rpe113x7r105050v c5 and c12 47 m f, 50v, alum - united chemicon 515d476m050 c9 and c10 6.8 m f, 50v, ceramin - mallory m60u6r8m50 c13 1nf, 100v, ceramin - kemet c322c102k1g5ca cr1 schottky diode - motorola mbrd360 l2 40 m h at 5a, pulse engineering pe - 53571 l3 4 m h at 5.5a, pulse engineering pe - 53570
7-70 HIP5061 390 m f, 50v, type 673d from united chemicon). this change would also greatly improve load transient response, pro- vided that the loop compensation is appropriately adjusted. note that in the circuit of figure 38, capacitor c12 does not signi?cantly affect output ripple, but is necessary to absorb the energy stored in l2 during severe load transients. in the event of a step change in load from 1.8a to 0a, c12 will limit the output voltage overshoot to about 10v and protect the drain of the dmos transistor from overvoltage breakdown. input and v dd filters since the boost converter is current fed, input ?ltering is eas- ily achieved by the addition of a small capacitor c4. this capacitor provides nearly 40db of ripple current attenuation for the input, reducing the ac ripple current ?owing into the converter to less than 200ma. r5 and c3 have been chosen to provide good ?ltering of high frequency pulse currents. r5 provides isolation between the analog v dd pin and the high pulse current v g pin, and also provides a means to control the turn-on speed of the dmos transistor by limiting the peak current available to the internal gate drive circuitry. thus the output transition time may be increased to prevent drain voltage undershoot. undershoot may result in activation of device parasitics and improper circuit operation. for the two-layer board used for this design, c3 could be reduced to 0.22 m f without affecting circuit operation. c5 was added to provide low-frequency ?l- tering at the v dd pin. this reduces the tendency of the circuit to oscillate off and on when the voltage at the v dd pin s in the vicinity of the under voltage lockout threshold, typically 10v, and the output power is high (30w - 50w). shunt regulator resistor resistor ra has been chosen to be as large as possible to reduce power dissipation at high line, while ensuring ade- quate v dd voltage at low line. note that the guaranteed range of input voltage for proper operation of this circuit is 11.2v to 15.3vdc, based upon data sheet limits. however, the circuit was found to perform well at room temperature for v i = 10.7vdc to 17vdc. the maximum value for ra is ra has been chosen as 20 w , which results in a current into the v dd clamp that is less than 105ma when the input volt- age is at its maximum: r max v imin , 10.5 C 0.033 ---------------------------------------- - 21 w == i max v imax , 13.3 C ? ?? 20.0 ------------------------------------------------- - 100ma == 105ma < snubber network a snubber network has been added to reduce the ringing at the drain due to parasitic layout inductances. in particular, under severe load transient conditions, this snubber is nec- essary to protect the drain from voltage breakdown. a sec- ond bene?t of reducing the noise and ringing at the drain is that it reduces the tendency of the HIP5061 to exhibit noise- related instabilities at high peak dmos transistor currents (4a-6a). a value of 1000pf was chosen for c13, since this is adequate to dampen the ringing associated with the 200pf drain capacitance of the dmos transistor. r11 was chosen as 7.5 w to provide the best possible dampening given the parasitic inductances that exist in the layout. note that this snubber may not be necessary if the layout of the circuit were improved, or if the application did not push the envelope of dmos transistor current. other power supply topologies figure 39 shows three other topologies besides the boost that may be implemented with the grounded source dmos power transistor used in the HIP5061. other, more complex power supply topologies such as the quadratic are also possible to implement with the HIP5061. one noteworthy feature of the quadratic topology as shown in figure 41 is the wide input to output voltage transfer ratio possible with reasonable duty cycles. duty cycles that are not near the minimum dmos tran- sistor on time speci?cation shown in the data sheet. this permits easier control at the extremes of the transfer ratios. compensating the control loop can pose challenges because of the wider changes in the transfer ratio and hence loop gain. the sepic topology [11,13] does not have quite as wide input- output voltage range with reasonably controlled duty cycles as the quadratic converter mentioned above, but it does allow both voltage increase and decrease with the same cir- cuit. this is particularly advantageous when a power supply is being used in the stabilizing mode and isolation is not required. for example, in an application where a regulated 24v output is required and the input voltage varies 20% from a nominal 24v. the sepic supply can provide both the boost and buck functions. another outstanding advantage of the sepic topology is its fault isolation of the input and output voltage. all energy is transferred via the coupling capacitor. moreover if the clock stops, voltage transfer stops. if the switching transistor shorts there is no output. the buck circuit will apply full input voltage to the load with a shorted transistor. this is reason that the sepic topology is referred to as the fail-safe buck.
7-71 HIP5061 figure 39a. sepic (fail-safe buck) converter figure 39b. cuk converter figure 39c. quadratic converter figure 39. three other topologies HIP5061 gate driver and control v dd v g drain fb v c gnd circuitry source v in v out + + - - HIP5061 gate driver and control v dd v g drain v c gnd circuitry source v in + - v out fb HIP5061 gate driver and control v dd v g drain fb v c gnd circuitry source v in v out + + - - figure 40. flyback converter it should be noted that when the cuk topology is imple- mented, a transistor current source is used to convert the negative output voltage of the cuk converter to a current that is level shifted to the fb terminal on the HIP5061. two other useful topologies that may be used are the for- ward and the flyback as shown in figure 40 and figure 41. as shown, they may either be operated as an isolated or non-isolated converter. figure 41. forward converter coupling means isolated or direct HIP5061 gate driver and control v dd v g drain fb v c gnd circuitry source v in v out + + - - coupling means isolated or direct HIP5061 gate driver and control v dd v g drain fb v c gnd circuitry source v in v out + + - -
7-72 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com HIP5061 both the sepic and the boost topologies may be operated at high voltages with the addition of a high voltage cascode . figure 42 shows the cascode sepic converter that is essentially limited by the selection of the external power transistor. the burden of voltage, and power is placed upon the external transistor. the HIP5061 still performs the drain current sampling and the control function is the same as the non cascode con?guration. figure 42. off line cascode sepic figure 43 shows the voltage transfer as a function of duty cycle for the power supply topologies discussed. figure 43. voltage transfer as a function of duty cycle for various topologies HIP5061 gate driver and control v dd v g drain fb v c gnd circuitry source 160v v out + + - - v in 100 10 1 0.1 0.01 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 m = v out /v in duty cycle (d) buck-boost, cuk and sepic m = d/(1-d) m = 1/(1 - d) boost quadratic m = d 2 /(1 - d) 2 buck m = d references [1] cassani, john c.; hurd, jonathan j. and thomas, david r., wittlinger, h.a.; hodgins, robert g.; sophisticated control ic enhances 1mhz current controlled regulator performance , high frequency power conversion (hfpc) conference proceedings, may 1992, pp. 167-173 [2] smith, craig d. and cassani, distributed power systems via asics using smt , surface mount technology, october 1990 [3] maksimovic and cuk, switching converters with wide dc conversion range , high frequency power conversion (hfpc) conference record, may 1989 [5] maksimovic and cuk, general properties and synthesis of pwm dc-to-dc converters , ieee power electronics specialists conference (pesc) record, june 1989 [6] sokal and sokal, class e - a new class of high ef?ciency tuned single-ended switching power ampli?ers , ieee journal of solid-state circuits, june 1975, pp. 168-176 [7] mansmann, jeff; shafer, peter and wildi, eric, maximizing the impact of power ics via a time-to-market cad driven power asic strategy , applied power and electronics conference and exposition (apec) proceedings, febru- ary 1992, pp. 23-27 [8] severns and bloom, modern dc-to-dc switchmode power converter circuits , van nostrand reinhold, 1985 [9] sum, k., switch mode power conversion - basic theory and design , marcel dekker, in., 1984 [10] pressman, a., switching and linear power supply, power converter design , hayden book co., 1977 [11] massey, r.p. and snyder, e.c., high voltage single- ended dc-dc converter , ieee power electronics spe- cialists conference (pesc) record, 1977, pp. 156-159 [12] clarke, p., a new switched-mode power conversion topology provides inherently stable response , power- con 10 proceedings, march 1983, pp. e2-1 through e2-7 [13] intersil application notes an9208 and an9212.1

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